FIG. 1 is a block diagram showing how digital data are processed by a conventional IC tester 10. When data are generated, tester controller 20 writes the data in memory 18 and each TVG (test vector generator) 16 reads the corresponding daza from memory 18 and generates a test vector at a specific time. This vector is then fed as signals through pin electronics 14 for the corresponding pin to a specific terminal of a DUT (device under test) 12. Master sequencer 26 controls the test sequence, such as the starting and stopping of the data generation, etc., between tester controller 20, memory 18 and several TVGs 16. A general purpose computer, such as a UNIX Work Station, is used for tester controller 20. The bandwidth of the bus from tester controller 20 to memory 18 is usually not as wide as that of the bus between each TVG 16 and memory 18 that is internally configured in the IC tester.
On the other hand, when data are evaluated, signals output from the DUT terminal are formatted to a specific level inside the corresponding pin electronics 14 and are then produced by TVG 16 as data, at specific times, and are stored in memory 18. Data stored in memory 18 are eventually read by tester controller 20. Tester controller 20 perform operations, then evaluates the data. Master sequencer 26 controls the test sequence, such as starting and stopping of data acquisition, etc., between tester controller 20, memory 18 and the several TVGs 16.
Although in the case of newer ICs it may be necessary to produce random data sequences and data of a larger period may be needed for the test, by means of the structure in FIG. 1, only tester controller 20 is able to write data in memory 18 and therefore, there is a disadvantage in that preparation for producing the data takes a long time. Moreover, if the data period is long and has not been entered in memory 18, the speed of data transfer from tester controller 20 to memory 18 is slow and real time DUT tests cannot be performed.
A new module for data generation that has a larger memory may also be developed, but the new development is expensive and takes a year or longer to develop. Consequently, other problems are encountered with development of ICs that use these modules.
Moreover, although some of the newest ICs for high speed communication must be tested in a condition of which the data header is long or the data part is long, it is difficult to discard the header in real time while the data are being read and stored only the long body of data. Therefore, once all of the data have been stored in the memory, the memory details are read in succession by the tester controller and the results are obtained. As a result, it takes time to transfer data to tester controller 20.
FIG. 2 is a block diagram of IC tester 30 with a conventional DSP (digital signal processing) function. Furthermore, unless otherwise noted, the same symbols and numbers are used for the same structural elements in the several Figures.
By means of the structure in FIG. 2, DSP part 2 is connected to memory 18 via local bus 24 as an addition to FIG. 1. Master sequencer 28 controls the test sequence between tester controller 20, memory 18, the several TVGs 16, and DSP part 22. By means of this structure, DSP part 22 can directly read and perform operations for the data in memory 18 and write data to memory 18. Therefore, there is a reduction in the items processed by Lester controller 20 and high-speed testing is possibe. Nevertheless, high-speed multifunctional DSP devices are expensive. Moreover, such high speed testing cannot be realized when the DSP part is not used as originally intended, for instance, when it is used for a bit operation such as a shift operation, etc. Further, since the DSP is controlled by a microprogram system, its capability is limited. For the aforementioned reasons, achieving high speed with a DSP only is a problem in terms of cost/performance.
A high-speed shift operation can be easily obtained if the proper hardware is available, but the cost of making a new ASIC (application-specific integrated circuit) is high, and it takes a year or longer to develop an ASIC. Further, this type of ASIC is used for special purposes and few are produced. Therefore, developing an ASIC is unacceptable in terms of both the cost and the development period. Even if the funds are available to develop an advanced ASIC, will probably become necessary to focus on the development of the next ASIC without recovering the cost of the previous ASIC because of the rapid progress of ICs to be tested.
IC test applications are often made in line with the stage of development of the IC, but because specifications of the IC often change before development is completed, there is also a problem that it will be necessary to become familiar with the changes in such specifications while keeping the detrimental effects on performance to a minimum when developing an ASIC.
On the other hand, a processing apparatus for special processing of data content that uses an FPGA (field programmable gate array) is described in Japanese Patent laid-open No. Heisei 6(1994)180,342 "IC Evaluation Device" with a laid-open date of Jun. 28, 1994 and Japanese Patent laid-open No. Heisei 9(1997)-6641 "Information Processing Apparatus" with a laid-open date of Jan. 10, 1997. The capability of these devices is limited in terms of high-speed generation or evaluation of data with a complex pattern and they cannot be used as a general-purpose digital data processing apparatus for IC testing.
Accordingly, it is an object of the present invention to solve the aforementioned problems by providing a general-purpose digital data processing apparatus for IC testers. IC test applications that are faster than those of conventional systems can be constructed for the general-purpose digital data processing apparatus for IC tests of the present invention by fewer man-hours, and these applications can be flexibly executed.
Another object of the present invention is to provide a general-purpose data processing apparatus equipped with a data-generation function or a data-evaluation function with a simple design so that one device can be flexibly reconfigured for several applications.
Another object of the present invention is to provide a general-purpose data processing apparatus for IC testing that uses a large memory and reconfigurable logic devices.
Yet another object of the present invention is to provide a data processing apparatus for IC testing that uses a high-speed memory, a DSP, and reconfigurable logic devices so that the DSP and reconfigurable logic devices are efficiently used, making high-speed execution of applications possible, and a reduction of the number of development processes possible.